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In 1973 a company called Mostek developed the Mostek MK4096, a chip with a capacity of 4 kilobytes. What made the MK4096 special was a rather clever idea called address multiplexing. On previous chips there was an address line (the simplest way to explain this rather complex thing is that it is essentially similar to the number outside your front door) per kilobyte, so a normal 4 kilobyte chip had 4 address lines and therefore 8 pins.

As chips would get bigger, the number of pins and address bars would need to increase, making the packaging larger and also increasing the power consumption. Mostek cut the number of pins and address lines in half and fed the pieces of the address line to the DRAM on successive clock cycles. This was a revolutionary idea and while some thought it was a waste, the guys at Mostek were proven to be geniuses. Mostek later went on to hold a staggering 75% of the DRAM market with its 16K chips but unfortunately for Mostek Japanese manufacturers started selling chips that employed the same address multiplexing but at much cheaper prices.

Time for Change

The Intel 1101, 1102, and 1103 all used the famous Dual In-line Pin package. The familiar looking chip with the even number of pins on either side was used as the de facto package for DRAM. Many packages were developed but none could compare the durability of the DIP package. In 1983 a new package was developed by a scientist working for Wang Laboratories. The new package was dubbed the Single In-line Memory Module or SIMM. While DIPs were rectangular and used an even amount of pins arranged in a manner that made them look like an insect, SIMMs were similar to current DDR2 and DDR3 in that they are thin boards on which the memory chips are mounted. These SIMMs slotted into sockets similar to current DDR memory sockets. SIMMs had many advantages over DIP but the main one was upgradability.

Motherboards that used DIP memory quickly became obsolete because they were limited to the size of DIP that they could support. SIMMs took the limitation away from the motherboard and onto the packaging itself. It was now the memory manufacturers’ job to cram as many memory chips as possible onto a module.

The first commercially used SIMM package had 30 pins and was used in 286, 386 and 486 systems. Each SIMM used an 8-bit (l byte) bus to communicate with the system and often had a capacity of between 256KB and 1MB, but did in fact reach up to 16MB. When the 486 systems had matured and the name Pentium was being whispered behind closed doors, a new SIMM package was being produced. The 72 pin SIMM had a bus size of 32 bits, which was exactly what the new processors needed. The capacity of 72 pin SIMMs broke past the 16MB limit of the 30 pin variant and reached a staggering 256MB. By the late 90s, the 72 pin SIMM had fully replaced the 30 pin SIMM.

SDRAM

There are two types of DRAM: Synchronous (SDRAM) and Asynchronous DRAM. Asynchronous DRAM has long since died out but used to be the basis for the original Video RAM that was used on video cards long since forgotten. Synchronous DRAM (SDRAM) is what current system memory is based on. Synchronous just means that instead of responding as quickly as possible to a request the memory waits for a clock signal before it will send data. This synchronization allows SDRAM to perform more complex operations than Asynchronous DRAM.

The first generation of SDRAM was SDR SDRAM. SDR stands for Single Data Rate and means that it can accept one command and transfer one word of data per clock cycle. The model numbers corresponded to clock frequencies, i.e. PC100 denoted that the SDR DRAM had a clock frequency of 100MHz (100 clock cycles per second). SDR DRAM was featured with three clock frequencies; 66MHz (PC66), 100MHz (PC100) and 133MHz (PC133). SDR DRAM used a 64 bit bus. SDR DRAM also introduced the Dual In-line Memory (DIM) module. For processors like the Pentium Pro, which used a 64-bit bus, the bus from the SIMMs had to be combined. It was crucial that SIMMs be seated in pairs, very much like today’s dual channel DDR2 and DDR3 kits, but unlike today’s kits if a module did not have a partner it would not function. DIMMs also do away with the redundancy featured in SIMMs. While SIMMs have 30 or 72 contacts on each side of the module, only one side is actually used (the other contact is there for redundancy). On DIMMs each contact is a separate electrical contact.

DDR SDRAM

Dual Data Rate SDRAM was a second generation version of SDRAM and unlike SDR, DDR is able to transfer data on the rising and falling edge of the clock cycle. This gives rise to the name Double Data Rate because it is able to transfer double the data that an SDR could do in a clock cycle. DDR DRAM modules were marketed under two systems. The first denotes the transfer rate, i.e. DDR-200 (200 million transfers per second). The second system is the labeling of modules according to maximum theoretical bandwidth i.e. PC-1600 (l600MB/s). The bandwidth (MB/s) for DDR modules is worked out with the following equation:

(Memory bus clock rate) x 2

(for dual rate) x 64

(number of bits transferred per cycle)

divided by 8 (number of bits/byte)

DDR reached a maximum capacity per module of 2GB and a clock frequency of 200MHz(DDR-400).

DDR2

DDR2 SDRAM, as the name suggests, is an improved version of DDR SDRAM. Able to transfer data at double the rate of its predecessor, DDR2 provided the bandwidth needed when multi-core processors were introduced. The memory bus speed runs twice as fast as the speed of the memory chips on the module, which means that during every clock cycle four words are written or read compared to DDR’s two per clock cycle.

DDR2 has a few benefits over DDR. The first is on-die termination. Unlike DDR which relied on transistors on the motherboard to eliminate excess signal noise, DDR2 has these transistors on each memory chip. Another benefit is the increased Prefetch size. RAM Prefetch is the amount of data a memory chip can call for from the system in preparation for work that is to be done. DDR’s Prefetch size is 2 bits while DDR2’s is 4 bits; this effectively means that DDR2 can request double the amount that DDR is able to. DDR and DDR2 memory cells send data to an I/O buffer. DDR does this at two transfers per clock; DDR2 sends data to the I/O buffer at four transfers per clock but at the same clock frequency of 100MHz just like DDR. The I/O buffer of DDR2 operates at double the frequency of a DDR I/O buffer (200MHz instead of 100MHz). The buffer then transmits the data at the speed of the data bus – for DDR the speed is 200Mbps while DDR2’s is 400Mbps. Therefore the memory bandwidth has increased but not the actual memory cell clock speed. The higher latency of DDR2 is caused by the memory chips themselves.

DDR2-533 chips are comparable to DDR-266 chips, which means that they could never compare to DDR-400 in terms of latency. DDR2-800 can compare to DDR-400 in latency terms because the memory chips used are similar to DDR-400 memory chips.

DDR2 uses less power (l.5V compared to DDR’s 2.5V). These voltage figures are the standard but can be increased for use in high performance memory.

DDR2 comes in five official speeds; DDR2-400, -533, -677, -800 and -1066. Bandwidth for DDR2 officially topped out at 8533MB/S.

Memory manufacturers noticed the demands of the overclocking fraternity and have released memory modules rated for higher than the JEDEC standard of DDR2-1066. Without the JEDEC ratification of speeds higher than DDR2-1066, memory module manufacturers cannot be held accountable for modules that don’t reach the advertised speeds.

DDR3

DDR3 was launched in 2007 and, while early adoption was slow, the rate has increased over the last year or so. DDR3 follows the trend and provides double the number of words written and read than DDR2. To date JEDEC has only standardized four speed rankings of DDR3: DDR3-800, -1066, -1333 and -1600. Like DDR2, the memory clock of DDR3 is 4 times slower than that of the bus, which increases the number of transactions that the memory can do. The top official JEDEC standard achieves a staggering 1600 million transfers per second with a bandwidth of 12 800MB/s but the unofficial modules have reached transfer rates of 2400 million transfers per second with bandwidth reaching the remarkable figure of 19 200MB/S. It is unknown when or if JEDEC will make these official.

DDR, DDR2 and DDR3 have all had the ability to benefit from dual channel arrangement, but with the launch of the Core i7 processors from Intel and the accompanying X58 platform, triple channel DDR3 has been adopted. The use of a triple channel memory configuration provides a large leap in bandwidth which is very beneficial to the new Core i7 processors.

Never Forget

DRAM has come a long way since its original inception and we have no doubt that it will evolve to provide data transfer rates and bandwidth that we cannot even dream of. But the pertinent questions are whether SDRAM will be able to fight off future challengers and whether the DRAM consortium will resort to underhanded tactics. The fact that SDRAM has survived for all these years is testament to the trust that the industry has in it.

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